This application relies for priority upon Korean Patent Application No. 1999-18342, filed on May 20, 1999, the contents of which are herein incorporated by reference in their entirety.
1. Field of the Invention
The present invention is in the field of data processing systems and is more specifically related to data processing systems capable of addressing expanded memories.
2. Description of Prior Art
Processor technology is developing at a rapid pace lead by precision manufacturing processes and the needs of new high performance applications. These applications are highly functional, and complex, occupying a large amount of storage. in memory devices. Typically, a microprocessor has a fixed memory capacity, for example, a 16-bit processor is limited to 64 kilobytes (Kb) of memory. To increase the available memory space in a 16-bit processor to 1 Mb, for example, a 20-bit memory address system is needed.
Several methods are known for expanding the memory address of a 16 bit processor, such as, segmentation, bank switching and use of memory management units (MMU).
MMUs use virtual addressing wherein the main memory is divided into pages. These pages, or memory addresses, can be divided into two parts, the page address and an offset within the page. The MMU takes a virtual address and uses the page address as an index to a page table. The page table contains a physical page address. This physical page is concatenated with the offset to produce the physical address, which is used to address the main memory. Despite the performance of MMUs, their disadvantages include, large size and expensive costs.
Prior art FIGS. 1A and 1B illustrate address expansion using segmentation. A 16-bit segment base address is transferred to 16-bit segment base register 12 through address bus 18. The 16-bit segment base address is converted to a 20-bit segment base address by shifting the least significant 4 bits to the left. A 16-bit offset address is stored in an offset register 14, and then converted to a 20-bit offset address by inserting a hexadecimal number xe2x80x9c0.xe2x80x9d Adder 16 generates a 20-bit expanded address by adding the 20-bit segment base address and offset address. However, the segmentation method shown in FIGS. 1A and 1B cannot be adapted to a processor system that has address accessing features other than a 16-bit system.
Prior art FIGS. 2A and 2B illustrate a bank switching address expanding method. Each memory bank is assigned a bank number. A main memory is divided into 16 memory banks. The bank number units, each consisting of four bits, select the 16 memory banks. A 16-bit base address is stored in address register 22 through address bus 25. A 16-bit offset address, stored in offset address 23, is added to the 16-bit base address in adder 26, and the sum is applied to combination logic block 27. The combination logic block 27 combines the 4-bit memory bank address supplied from bank number register 24 with the summed 16-bit address supplied from the adder 26, and then transfers the combined result, i.e., a 20-bit expanded address, to address bus 28. In the bank switching process, same interrupt routines are stored in the same regions of the memory banks when an interrupt occurs, or an independent bank switching is carried out as each memory bank is activated by its own program. Since the switching operation for each memory bank is enabled while a program is running, codes assigned to switching for the same region in a memory cannot be changed. Thus, such a switching feature has many limitations in a system employing an interrupt service routine.
In a von Neumann machine, like those described above, the program and the data occupy the same memory. The machine has a program counter (PC) which points to the current instruction in memory. The PC is updated on every instruction. When there are no branches, program instructions are fetched from sequential memory locations. A majority of commercial processors use von Neumann architecture.
Unlike von Neumann architecture, Harvard architecture has a separated memory structure, i.e., a program memory and a data memory. It is difficult to provide an expanded address for both the program and data memories.
Therefore, a need exists for a reliable system and method for expanding a 16-bit memory address built on current hardware.
There are two ways to expand addressing with 16-bit processors; one is to create new instructions for the expanded addresses and the other is to establish combination codes from existing instructions.
In order to expand addressing by creating new instructions, instructions relevant to addressing memory locations or defined instruction sets involving frequently used instructions are needed. Even though creation of new instructions maintains the adaptability of the processor without modifying existed instructions, it causes a topological burden on hardware construction in CISC (Complex Instructions Set Computer) microprocessors. In these processors, almost all instructions are referred to their own memories. Another possibility is the creation of the instructions only for frequently used instructions for the purpose of reducing the topological burden on hardware. However, this approach limits the actual number of instructions available to perform the expanded address modes.
Alternatively, combination codes can be employed. In this approach a bank register is set up by instruction LOAD, and subsequent instructions are carried out in a selected memory bank after an address stored in the bank register is assigned to the most significant address of the memory bank. While this method does not burden the hardware topology, an arrangement of instructions for saving and restoring addresses of the bank registers, SAVE/RESTORE, becomes complicated when instructions for calling subroutine and returning, CALL/RET, are active, and addresses of the bank registers cannot be stored therein during a bank interrupt. Further, it is difficult to access a data memory in a Harvard processor having a divided memory structure of program and data memories.
Therefore, a need exists for a 16-bit (2-byte) memory addressing system, which can efficiently be expanded to accommodate 24-bit (3byte) addresses using existing processor systems. This system is more desirable than an instruction structure modified to 24-bit (3-byte), for expanded addressing because a 24-bit structure cannot handle conventional 16-bit code.
Additionally, a need exists for a system and method of setting existing instructions into instructions for normal addresses, and new instructions for the expanded address areas are created therein. Further, a programmable control unit in a microprocessor is needed to detect whether an external instruction is the normal address mode instruction or the expanded address mode instruction, and then perform a control operation.
It is an object of the invention to provide a microprocessor system capable of accessing an expanded address structure.
It is another object of the invention to provide a von Neumann microprocessor system capable of accessing an expanded address structure for a data memory.
It is another object of the invention to provide a Harvard microprocessor system capable of accessing an expanded address structure for program and data memories.
In order to accomplish these objects, a microprocessor according to one embodiment of the present invention includes: a control unit for determining whether an external instruction is to be used for a normal address mode or to be used for a expanded address mode and for generating control signals; a program counter for generating a first address in response to an output from the control unit during the normal and expanded address modes; an address generator for generating a second address during the expanded address mode, in response to an output from the control unit; an address bus for transferring the first address out of the microprocessor; and a data bus for transferring the second address out of the microprocessor.
The microprocessor also includes an address interface circuit for transferring the second address out of the microprocessor through the data bus. The address interface circuit includes: an address register for storing the second address supplied through the data bus; and a latch circuit for holding the second address stored in the address register therein. The control unit makes an external interrupt be inhibited until the first and second addresses are transferred out of the microprocessor when the external instruction is to be used for the expanded address mode.
In another embodiment of the present invention, a microprocessor includes: a control unit for determining whether an external instruction is to be used for a normal address mode or to be used for a expanded address mode and for generating control signals; a program counter for generating a first instruction address in response to an output from the control unit during the normal and expanded address modes; an address generator for generating a first data address during the normal and expanded address modes, and for generating a second instruction address and a second data address during the expanded address mode, in response to an output from the control unit; an instruction address bus for transferring the first instruction address out of the microprocessor; a data address bus for transferring the first data address out of the microprocessor; and a data bus for transferring the second instruction and data addresses out of the microprocessor. An address interface circuit employed in the microprocessor, for transferring the second instruction and data addresses out of the microprocessor through the data bus, includes: an instruction address register for storing the second instruction address supplied through the data bus; a first latch circuit for holding the second instruction address stored in the instruction address register therein; a data address register for storing the second data address supplied through the data bus; and a second latch circuit for holding the second data address stored in the instruction address register therein.